PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 171

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

8.1.1.3
Characteristics: address recognition high byte.
Only the high byte of a 2-byte address field will be compared. The address byte is
compared with the fixed value FE
individually programmable values RAH1 and RAH2 in the RADR register. The whole
frame excluding the first address byte will be stored in the SCC receive FIFO.
The address bytes can be masked to allow selective broadcast frame recognition.
8.1.1.4
Characteristics: no address recognition
No address recognition is performed and each complete frame will be stored in the SCC
receive FIFO.
8.1.2
PPP (as described in RFC1662) can work over 3 modes: asynchronous HDLC,
synchronous HDLC, and octet synchronous. The DSCC4 supports asynchronous HDLC
PPP over ISDN or DDS circuits as well as synchronous HDLC PPP for use over dial-
up connections. The octet synchronous mode of PPP protocol (RFC 1662) supports PPP
over SONET applications.
Both the asynchronous HDLC PPP mode, as well as the synchronous HDLC PPP
modes, are submodes of the HDLC mode. Either mode is selected by configuring the
DSCC4 for the standard HDLC mode. In addition the appropriate PPP mode is selected
via bit field ’PPPM’ in register CCR2.
The DSCC4 provides logic to convert an HDLC frame to an ASYNC character stream
with the specified mapping functions. Layer 3 PPP functions are normally implemented
in software.
The PPP-support hardware allows software to perform segmentation and reassembly of
PPP payloads, and allows the DSCC4 to perform the asynchronous HDLC PPP or the
synchronous HDLC PPP protocol conversions as required for the network interface.
8.1.2.1
The DSCC4 transfers a data block from the shared memory, inserts HDLC Header
(Opening Flag), and appends the HDLC Trailer (CRC, Ending Flag). Zero-bit stuffing
algorithm is also performed. No character mapping is performed. The bit-synchronous
PPP mode differs from the HDLC mode (address mode 0) only in the abort sequence:
HDLC requires at least 7 ’1’ bit whereas PPP requires at least 15 ’1’ bit abort sequence.
Data Sheet
Address Mode 1
Address Mode 0
HDLC/PPP Protocol Mode
Bit Synchronous PPP
H
or FC
171
H
(group address) as well as with two
Detailed Protocol Description
PEB 20534
PEF 20534
2000-05-30