PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 77

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Receive:
• If the current receive buffer descriptor has its HOLD-bit set and the current data buffer
Data Sheet
and the next descriptor address of the current descriptor again. The DMAC branches
to the next descriptor address if HOLD bit has been reset to ’0’.
There are three methods to handle the situation in which the next descriptor address
pointer is not yet valid in the current transmit descriptor. This happens if the location
of the next descriptor is not known when preparing the last descriptor of the chain:
1.Updating the next descriptor address before providing transmit poll request
command.
2. Updating BTDA address in register CHiBTDA followed by a channel initialization
command (’IDT’).
3. Programming the "next transmit descriptor address" of each descriptor with HOLD
bit set pointing to a fixed dummy descriptor with byte number 0 (NO = 0). The next
descriptor address of the dummy descriptor can be programmed to point to a newly
prepared descriptor list before providing a transmit poll request command. The DMA
channel will continue branching to the dummy descriptor, completing it without data
transfer and branch to the next descriptor which itself might point to the dummy
descriptor again if HOLD bit is set.
has been filled, the DMA channel does not branch off to the next descriptor. An active
“HOLD” bit causes a receive FIFO overflow to occur. If more data are received, those
are discarded by the serial channel.
Furthermore an error interrupt is generated anytime a receive channel detects the
HOLD condition.
The Host CPU (software) is expected to prepare sufficient amount of receive
descriptors which is supported by several control mechanisms. Thus detecting a Hold
condition in the receive descriptor list is treated as an exceptional condition by the
corresponding DMA channel.
Once, the DSCC4 has detected the HOLD=’1’ condition in receive direction, an
interrupt is generated after completion of the current receive descriptor and the
corresponding DMA channel is deactivated for receive direction as long as the host
does not request an initalization via action request command in register GCMDR. The
data transfer can be restarted by setting the AR bit in the GCMDR register after the
channel specific configuration register has been updated (new initialization).
77
DMA Controller and Central FIFOs
PEB 20534
PEF 20534
2000-05-30