PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 79

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

descriptor address is stored in register FTDA/FRDA as the (current) first descriptor
address. With branching to the next descriptor the first descriptor address register is
updated. Thus the host can keep track of the DMAC’s progress by reading the FTDA/
FRDA register. Beside the base descriptor address the user provides the Last Tx/Rx
Descriptor Address in the corresponding LTDA/LRDA register. After transferring all data
from the current data section and before branching to the next descriptor, the DMAC
compares FTDA/FRDA and LTDA/LRDA. If the corresponding addresses are not
identical the DMA channel branches to the next descriptor and the FTDA/FRDA register
is updated with “next descriptor address“ to continue normal transfer operation. If a
match occurs the DMA channel is suspended until the host writes a new last transmit/
receive descriptor address to LTDA/LRDA register. After write access to these registers
the DSCC4, again, compares FTDA/FRDA and LTDA/LRDA and proceeds as described
above.
• In transmit direction the condition LTDA equal to FTDA corresponds to the transmit
• In receive direction the condition LRDA equal to FRDA corresponds to the receive
There are three methods to handle the situation in which the next descriptor address
pointer is not yet valid in the current transmit descriptor. This happens if the location of
the next descriptor is not known when preparing the last descriptor of the chain:
1. Programming the "next descriptor address" of each last descriptor pointing to a newly
2. Updating BTDA/BRDA address in register CHiBTDA/CHiBRDA followed by a channel
3. Programming the "next descriptor address" of each last descriptor pointing to a fixed
Data Sheet
HOLD condition in HOLD bit controlled mode. In this case updating register LTDA is
the equivalent operation to transmit poll request command.
HOLD condition in HOLD bit controlled mode. Updating register LRDA will cause the
DMA channel branching to the next receive descriptor. No new initialization command
’IDR’ is necessary as in HOLD bit controlled mode.
Re-initialization might be necessary if the linked list does not continue at the "next
descriptor address" of the last descriptor but on any other address.
prepared descriptor list before updating register LTDA/LRDA. After write access to
LTDA/LRDA register, the DMA controller reads the next descriptor address again and
branches to the new descriptor.
initialization command (’IDT’/’IDR’).
dummy descriptor with byte number 0 (NO = 0). The next descriptor address of the
dummy descriptor must be programmed to point to a newly prepared descriptor list
before updating register LTDA/LRDA. The DMA channel will branch to the dummy
descriptor, completing it without data transfer, then branch to the next descriptor which
itself might point to the dummy descriptor again.
79
DMA Controller and Central FIFOs
PEB 20534
PEF 20534
2000-05-30