PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 265

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Table 59
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Data Sheet
Bit 31
Bit 15
CHiBTDA
30
14
CHiBTDA:
Channel i Base Transmit Descriptor Address Register (i=3...0)
i = 3...0
These registers determine the base address of the channel specific
transmit descriptor chain and can be located anywhere in the 32 bit
address range.
Note: The descriptor base addresses must be 32-bit aligned, i.e. bit 1
29
13
28
12
and 0 must be set to ’0’.
read/write
0000 0000
Channel 0
0058
written by CPU
evaluated by DSCC4
27
11
H
26
10
H
CHiBTDA(15:2)
Channel 1
0064
25
9
CHiBTDA(31:16)
H
24
265
8
23
7
Channel 2
0070
22
6
H
Detailed Register Description
21
5
20
4
Channel 3
007C
19
(TX Channel 3...0)
3
H
18
2
PEB 20534
PEF 20534
2000-05-30
17
1
0
16
0
0