PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 236

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Data Sheet
IMAR
AR
Interrupt Mask Action Request
On any action request, the DSCC4 will generate either an ’action request
acknowledge’ or an ’action request failed’ interrupt vector which is
transferred into the configuration interrupt queue. These interrupts can
be masked via bit ’IMAR’:
IMAR=’0’
IMAR=’1’
Action Request
Self-clearing command bit:
AR=’0’
AR=’1’
’action request acknowledge’ and ’action request failed’
interrupt vectors respectively are generated and
transferred into the configuration interrupt queue.
(Reset value)
’action request acknowledge’ and ’action request failed’
interrupt vectors respectively are NOT generated (and
thus NOT transferred into the configuration interrupt
queue).
No action request is performed.
If this bit is set to ’1’, the DMA controller will evaluate:
• register GCMDR for all interrupt queue configuration
• all DMA channel specific configuration registers
Any command (command bit set to ’1’) will cause the
corresponding configuration process to start.
A ’action request acknowledge’ or ’action request failed’
interrupt is generated after completion of all configuration
processes and a corresponding status bit is set in register
GSTAR.
commands;
(CHiCFG, i=3...0) for reset and initialization commands.
236
Detailed Register Description
PEB 20534
PEF 20534
2000-05-30
(-)
(-)