PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 423

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Table 122
No. Parameter
43
44
45
46
47
48
49
50
51
63
52
53
54
55
56
57
58
59
60
64
Note: T
Data Sheet
LA to LCLKO delay
LCSO active to LCLKO delay
LCSO inactive to LCLKO delay
LRD pulse width
LRD, LWR inactive to LCLKO delay
LD to LCLKO setup time
LD to LCLKO hold time
LRD, LWR active to LCLKO delay
LRD active to cycle start delay
cycle end to next cycle start delay
LCSO active to LCLKO delay
LCSO inactive to LCLKO delay
LWR active to LCLKO delay
LWR pulse width
LRD, LWR inactive to LCLKO delay
LD valid after LCLKO delay
LD hold after LCLKO delay
LD to LWR inactive delay
LD tristate delay after LCLKO
LWR active to cycle start delay
LA to LCLKO delay
cycle end to next cycle start delay
MCTC is the number of master clock wait states (in LBI clock cycles) selected in
register LCONF.
T
LRDY control signal if enabled via bit ’RDEN’ in register LCONF.
T
LBICLK
LRDY
PCICLK
is the number of additional wait states (in LBI clock cycles) introduced by
is the LBI clock time period which depends on the LBI clock division factor.
is the PCI clock time period.
LBI Timing (synchronous, de-multiplexed bus)
423
min.
5
5
5
5
5
5
5
5
5
5
1 T
+ 5
5
2T
2T
2 T
5 T
LBICLK
LBICLK
PCICLK
Electrical Characteristics
LBICLK
LBICLK
Limit Values
1 T
1 T
1 T
+MCTC+T
+MCTC+T
PCICLK
LBICLK
LBICLK
max.
20
20
20
20
0
25
20
20
20
20
20
20
1 T
+ 20
1 T
+ 20
20
PCICLK
PCICLK
PEB 20534
PEF 20534
LRDY
LRDY
2000-05-30
Unit
ns
ns
ns
(ns)
ns
ns
ns
ns
(ns)
ns
ns
ns
ns
(ns)
ns
ns
ns
(ns)
ns
(ns)
ns
(ns)