PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 277

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Data Sheet
RRES
STI
Receiver Reset Command
Self-clearing command bit:
RRES=’1’
Start Timer Command
Self-clearing command bit:
HDLC Automde:
In HDLC Automode the timer is operating in ’internal timer mode’. The
timer is started automatically by the SCC when an I-Frame is sent out
and needs to be acknowledged.
If the ’STI’ command is issued by software:
STI=’1’
All protocol modes except HDLC Automode:
In these modes the timer is operating in ’external timer mode’.
STI=’1’
The SCC receive FIFO is cleared and the receiver
protocol engines are reset to their initial state.
The SCC receive FIFO accepts new receive data from the
protocol engine immediately after receiver reset
procedure.
It is recommended to disable data reception before
issuing a receiver reset command by setting bit
CCR2.RAC = ’0’ and enabling data reception afterwards.
A ’receiver reset command’ is recommended after all
changes in protocol mode configurations (switching
between protocol the engines HDLC/ASYNC/BISYNC or
sub-modes of HDLC).
An S-Frame with poll bit set is sent out and the internal
timer is started expecting an acknowledge from the
remote station via an I- or S-Frame.
The timer is stopped after receiving an acknowledge
otherwise the timer expires generating a timer interrupt.
This commands starts timer operation in ’external timer
mode’.
The timer can be stopped by rewriting register TIMR. If the
timer expires a timer interrupt is generated.
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Detailed Register Description
PEB 20534
PEF 20534
(all modes)
(all modes)
2000-05-30