PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 33

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Table 1
Pin No.
25
29
32
Data Sheet
Symbol
IRDY
TRDY
STOP
PCI Bus Interface(DEMUX Interface) (cont’d)
Input (I)
Output (O)
s/t/s
s/t/s
s/t/s
Function
Initiator Ready
IRDY indicates the bus master's ability to
complete the current data phase of the
transaction. It is used in conjunction with
TRDY. A data phase is completed on any
clock where both IRDY and TRDY are
sampled asserted. During a write, IRDY
indicates that valid data is present on
AD(31:0). During a read, it indicates the
master is prepared to accept data. Wait cycles
are inserted until both IRDY and TRDY are
asserted together.
When DSCC4 is Master, IRDY is an output.
When DSCC4 is Slave, IRDY is an input.
IRDY is updated and sampled on the rising
edge of CLK.
Target Ready
TRDY indicates a slave's ability to complete
the current data phase of the transaction.
During a read, TRDY indicates that valid data
is present on AD(31:0). During a write, it
indicates the target is prepared to accept data.
When DSCC4 is Master, TRDY is an input.
When DSCC4 is Slave, TRDY is an output.
TRDY is updated and sampled on the rising
edge of CLK.
Stop Signal
STOP is used by a slave to request the current
master to stop the current bus transaction.
When DSCC4 is Master, STOP is an input.
When DSCC4 is Slave, STOP is an output.
STOP is updated and sampled on the rising
edge of CLK.
33
Pin Descriptions
PEB 20534
PEF 20534
2000-05-30