PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 195

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

• after the end of a character currently being transmitted if the transmitter is not in IDLE
Transmission via this register is possible even when the transmitter is in XOFF state
(however, CTS must be ‘low’).
The TIC value is an eight-bit value. The number of significant bits is determined by the
programmed asynch character length. Parity value (if programmed) and selected
number of stop bits are automatically appended, equal to the characters provided via the
transmit data buffer. The usage of TIC is independent of in-band flow control
mechanism, i.e. is not affected by bit ’FLON’ in register CCR2 anyway.
To control multiple accesses to register TICR, an additional status bit STAR:TEC (TIC
Executing) is provided which signals that the transmission command of currently
programmed TIC is accepted but not yet completely executed. Further access to register
TIC is only allowed if bit STAR:TEC is ‘0’ again.
8.2.4.3
Transmitter:
The transmitter output is enabled if CTS signal is ‘LOW’ AND the XON state is reached
in case of in-band flow control is enabled. If the in-band flow control is disabled
(CCR2:FLON = ‘0’), the transmitter is only controlled by the CTS signal.
Nevertheless setting bit CCR1:FCTS = ‘1’ allows the transmitter to send data
independent of the condition of the CTS signal, the in-band flow control (XON/XOFF)
mechanism would still be operational if enabled via bit CCR2:FLON = ‘1’.
Receiver:
For some applications it is desirable to provide means of out-of-band flow control to
indicate to the far end transmitter that the local receiver’s buffer is getting full.
This flow control can be used between two DTEs as shown in figure 72 and between a
DTE and a DCE (MODEM) as shown in figure 73 that supports this kind of bi-directional
flow control.
Setting bit CCR1:FRTS = ‘1’ and CCR1:RTS = ‘0’ invokes this out-of-band flow control
for the receiver. When the shadow part of the SCC receive FIFO has reached a pre-
defined threshold of 20 bytes, the RTS signal is forced inactive (HIGH). When the
shadow part of the receive FIFO is empty, the RTS is re-asserted (‘LOW’). Note that the
data is immediately transferred from the shadow receive FIFO to the DMA accessible
FIFO (as long as there is space available). Thus when the shadow FIFO reaches the
20 bytes threshold, there are 4 more bytes storage available before an overflow can
occur. This provides sufficient time for the far end transmitter to react to the change in
the RTS signal and stop sending more data.
Data Sheet
the transmitter returns to IDLE state after transmission of the TIC and an ALLS (All
Sent) interrupt will be generated.
state. This does not affect the contents of the transmit FIFO. Transmission of
characters from transmit FIFO is resumed after the TIC is send out.
Out-of-band Flow Control
195
Detailed Protocol Description
PEB 20534
PEF 20534
2000-05-30