PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 204

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Table 28
Step
1
2
3
4
5
For the SCC, first, the serial mode, the configuration of the serial port and the clock mode
have to be defined. The host may switch the SCC between power-up and power-down
mode. This has no influence upon the contents of the registers, i.e. the internal state
remains stored. In power-down mode, however, all internal clocks are disabled, no
interrupts are forwarded to the host. This state can be used as a standby mode, when
the SCC is temporarily not used, thus substantially reducing power consumption.
Table 29
Step
1
2
3
Data Sheet
Action
Set clock mode specific features: CCR0, BRR, TTSA, RTSA, TPCMM,
RPCMM.
Set serial mode (HDLC, ASYNC, BISYNC): CCR0
Set serial port configuration (Encoding, output driver select, handshaking
mechansim): CCR0, CCR1
Action
Select
GMODE.CMODE bit.
GMODE.CMODE = ’0’
(causes the DMAC to check
HOLD bit before branching
to next descriptor).
Select FIFO size and thresholds: FIFOCR1...4
Set base descriptor addresses: BRDA, BTDA.
Verify/set HOLD=’1’ in last
element of linked list.
Configure channels: CHiCFG
- Interrupt Mask (RFI, TFI, RERR, TERR)
- DMAC Command (RDR, RDT, IDR, IDT)
Initialization of DMAC (Data Channels)
Initialization of the SCC(s)
Control
Mode
of
GMODE.CMODE = ’1’
(causes
compare FTDA/FRDA and
LTDA/LRDA before branch-
ing to next descriptor).
Write last transmit/receive
descriptor address to LTDA/
LRDA register.
the
204
DMA
Reset and Initialization Procedure
the
controller
DMAC
via
to
In parallel
prepare linked
list(s) in shared
memory.
PEB 20534
PEF 20534
2000-05-30