PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 367

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Note: The transmit interrupt notifies the CPU about the start of a transmission.
Example
To check for transmit errors only:
SSCIM(bit 1)=‘1‘, SSCCON(bit 8)=‘1‘, SSCCON(bit 10)=‘0‘,SSCCON(bit 11)=‘0‘
Data Sheet
IMRX
IMER
IMTX
The receive interrupt notifies transfer of the received data to the shared memory.
The error interrupt notifies the CPU about different error conditions related to data
transmission and reception. To further specify what sort of error interrupt the user
wants to trace, the corresponding bits of the SSC control register SSCCON has to
be set. The SSC error conditions that can be checked are transmit errors
(SSCCON(bit 8) =‘1‘), phase errors (SSCCON(bit 10)=‘1‘) and baud rate errors
(SSCCON(bit 11)=‘1‘). If any of these error conditions shall not be checked, the
corresponding enable bit has to be set to ‘0‘.
SSC Receive Interrupt Mask
This bit enables/disables receive interrupt indications:
IMRX=’0’
IMRX=’1’
SSC Error Interrupt Mask
This bit enables/disables error interrupt indications:
IMER=’0’
IMER=’1’
SSC Transmit Interrupt Mask
This bit enables/disables transmit interrupt indications:
IMTX=’0’
IMTX=’1’
SSC receive interrupts are disabled.
SSC receive interrupts are enabled.
SSC error interrupts are disabled.
SSC error interrupts are enabled.
SSC transmit interrupts are disabled.
SSC transmit interrupts are enabled.
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Detailed Register Description
PEB 20534
PEF 20534
2000-05-30
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(-)
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