PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 86

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Table 16
Offset
Addr.
0048
Data Sheet
H
Access
Type
r/w
Bit-Fields
Pos.
31..27,
26..22,
21..17,
15..11
7,5,3,1
6,4,2,0
Central FIFO Control Registers (cont’d)
Controlled
by
CPU
Name
TFR
THRESH0,
TFR
THRESH1,
TFR
THRESH2,
TFR
THRESH3,
M4_i
M2_i
Reset
Value
00000000
Default
0,
0,
0,
0
0
0
86
H
Register Name
FIFOCR2:
FIFO Control Register 2
Description
Transmit FIFO Refill Threshold i (i=0..3)
Transmit FIFO Refill Threshold for the
corresponding channel i in number of
DWORDs multiplied by its respective
multiplier Mx_i.
This threshold controls DMAC operation
towards the Host memory. A watermark
is calculated by:
watermark = TFRTHRESHi*Mx_i+1.
As soon as the number of valid data in
the transmit FIFO section is less than the
watermark, the DMA controller requests
for new data from shared memory.
Multiplier 4
Multiplier 2
DMA Controller and Central FIFOs
PEB 20534
PEF 20534
2000-05-30