PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 78

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

5.1.2.4
This mode is selected by setting bit CMODE=’1’ in register GMODE (see
Global Mode Register” on Page
The DMA controller operates on linked lists with pointer information stored in the DSCC4
internal configuration section.
The initialization procedure as well as the CPU to DSCC4 handshaking is equal to the
HOLD-Bit control mode as described in
The host CPU does not take care about the HOLD bit. The address of the descriptor in
the chain at which a ’Hold’ is to be exercised is written to the corresponding LTDA/LRDA
register. The DMA channel compares its current (first) descriptor address to LTDA/
LRDA. When a match occures, a ’Hold’ condition is activated. After attaching at least one
new descriptor to the linked list. Also the DMA channel does not take care on the HOLD
bit within the descriptors but compares its current descriptor address with LTDA/LRDA
register value. In case of address match this condition is equal to the HOLD-condition.
Figure 17
After initialization the DMAC internally starts with the Base Tx/Rx Descriptor Address
BTDA/BRDA as the “first descriptor address“ since this address points to the first
descriptor of the linked list that has to be processed by the DMA channel. The current
Data Sheet
DSCC4 Register
*) FTDA starts with BTDA and is updated by the DSCC4 until FTDA=LTDA
**) FRDA starts with BRDA and is updated by the DSCC4 until FRDA=LRDA
CHiFRDA**)
CHiFTDA*)
CHiBTDA
CHiLRDA
CHiBRDA
CHiLTDA
DMAC Operation Using Last Descriptor Address Control Mode
Data Transfer controlled via first and last descriptor addresses
Shared Memory
241).
Chapter 5.1.2.3
78
DMA Controller and Central FIFOs
with the following exception:
PEB 20534
PEF 20534
“GMODE:
2000-05-30