PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 87

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Table 16
Offset
Addr.
004C
Data Sheet
H
Access
Type
r/w
Bit-Fields
Pos.
6..0
8
7
Central FIFO Control Registers (cont’d)
Controlled
by
CPU
Name
RF
THRESH
M4
M2
Reset
Value
00000000
Default
0
0
0
87
H
Register Name
FIFOCR3:
FIFO Control Register 3
Description
Receive FIFO Threshold
Receive FIFO Threshold in number of
DWORDs. A watermark is calculated by:
watermark = RFTHRESH*M_x.
When more data than specified by this
watermark is available in the receive
FIFO the DMA controller is requested to
transfer data to the channel specific data
buffers in host memory until the receive
FIFO is empty.
Multiplier 4
Multiplier 2
DMA Controller and Central FIFOs
PEB 20534
PEF 20534
2000-05-30