PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 223

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

of the additional locations 64-255 are used, nevertheless the DSCC4 responds to
configuration read/write cycles within the address range 00
These configuration registers are addressed only using the PCI Configuration read/write
cycles and using the IDSEL/DEVSEL handshake signals.
The PCI Configuration Space is also valid in de-multiplexed bus interface mode, i.e. pin
DEMUX connected to V
Configuration register set on read/write transactions.
The Base Address fields in the configuration space define the memory base addresses
and the corresponding address range the DSCC4 will respond to. The first Base
Address is the base address of the DSCC4’s on-chip register range (Global control
registers, SCC registers, LBI control registers, GPP Control registers, SSC registers).
The second Base Address is the base address of the memory mapped LBI address
space.
According to the PCI Specification, mapped address ranges are evaluated by writing all
ones to the base address registers and reading back the value. The number of leading
zeros determine the supported address range:
Table 40
10
14
The status/command register (offset address 04
describes and determines the DSCC4 PCI system behavior and is described in details
in
Data Sheet
Offset
Address
Table
H
H
41:
Register Register Read Value
BAR1
BAR2
PCI Base Address Ranges
(after writing 0xFFFFFFFF
0xFFFFF800
0xFFFF0000
DD3
. In this case only signal IDSEL is used to select the PCI
H
H
223
H
)
H
) of the PCI Configuration Space
Supported Address Range
2 KByte
(DSCC4 on chip registers)
64 KByte
(Local bus address range mapped
to PCI (HOST) address space)
Detailed Register Description
H
to FC
H
.
PEB 20534
PEF 20534
2000-05-30