PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 158

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

7.5
Special events in the SCC are indicated by interrupts either for receive direction or for
transmit direction. Accordingly individual transmit and receive interrupt queues located
in the shared memory are provided for each of the 4 SCCs. The interrupts generated by
the SCC are forwarded as interrupt vectors to the channel specific and direction specific
interrupt queues. See
Vector” on Page
Each interrupt indicated by the interrupt vector or interrupt status register (ISR) can
selectively be masked (disabled) by setting the corresponding bit in the interrupt mask
register IMR.
Note: A dedicated transmit interrupt vector may contain receive interrupt indications. In
Note: A dedicated receive interrupt vector may contain transmit interrupt indications. In
In interrupt visible mode (CCR0:VIS = ’1’), masked interrupt status bits neither activate
the interrupt signal nor generate an interrupt vector, but are indicated in the respective
interrupt status register ISR.
This mode is useful when some interrupt status bits are to generate an interrupt vector
and other status bits are to be polled in the individual interrupt status register.
When using visible mode, only unmasked interrupt status bits are reset when the
interrupt status register is read.
Data Sheet
that case the receive interrupt indications can be ignored, since a dedicated
receive interrupt vector is generated, additionally.
that case the transmit interrupt indications can be ignored, since a dedicated
transmit interrupt vector is generated, additionally.
SCC Interrupt Interface
393.
“Interrupt Queue Overview” on Page 387
Serial Communication Controller (SCC) Cores
158
and
“SCC Interrupt
PEB 20534
PEF 20534
2000-05-30