PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 216

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Table 37
Register
GCMDR
DSCC4 performs the configuration and requests for the bus to transfer a CFG
interrupt vector to the IQCFG in shared memory
GSTAR
GSTAR
1st entry of
IQCFG in
shared memory
CCR0 (SCC1)
CCR1 (SCC1)
CCR2 (SCC1)
IMR (SCC1)
CMDR (SCC1)
Data Sheet
Register Initialization for HDLC Transparent Mode 0, Test Loop
Access
<= (write)
=> (read)
<=
=>
<=
=>
<=
<=
<=
<=
<=
Value
2220 0001
0020 0001
0020 0001
A000 0001
8000 0016
0204 8100
0803 0008
FFFA EF3D Interrupts are enabled as follows:
0101 0000
216
Meaning
Command Bits:
- Configure IQ SCC1 RX
- Configure IQ SCC1 TX
- Configure IQ CFG
- Action Request
Indication Bits:
- CFG interrupt indicated
- Action Request Acknowledge indicated
Acknowledge the interrupt indications:
- CFG interrupt
- Action Request Acknowledge
Indication Bits:
- CFG interrupt queue ID
- Action Request Acknowledge indicated
Power Up
NRZ
HDLC
Clock Mode 6b, assuming that a clock is
provided on XTAL1
TxD output driver select
HDLC Transparent Mode 0
Test Loop
FCTS=’1’
Receiver active
Continuous FLAG sequences as
interframe time fill
RFTH=’011’ (default value)
ALLS, XDU, XPR, RDO, RFS, RFO
Commands:
- Transmitter Reset
- Receiver Reset
Reset and Initialization Procedure
PEB 20534
PEF 20534
2000-05-30