PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 65

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

The CPU prepares linked lists for transmit and receive channels in the shared memory.
These may be handled by dynamically allocating and linking descriptors and buffers as
needed during runtime or by static predefined memory structures e.g. ring-chained-lists
(the ’last’ descriptor points back to the first descriptor). A mix of predefined descriptor
lists but dynamically handled data buffers may also be an appropriate solution. This
strategy depends on the specific application. The DMAC provides multiple control
mechanisms supporting all of these combinations in an efficient way.
The descriptors and data buffers can be stored in separate memory spaces within the
32-bit address range allowing full scatter/gather methods of assembling and
disassembling of packets.
Each descriptor contains a ’next descriptor address’ field to realize the linked list.
Because the DMA controller cannot distinguish between valid and invalid addresses, a
’Hold’ mechanism is needed to prevent the DMA controller from branching to invalid
memory locations. A ’next descriptor address’ might be invalid for several reasons:
• no further transmit transaction is requested; therefore no further transmit descriptor is
• temporarily the software is not able to attach new receive descriptors to the list in time;
• the receive descriptor list is organized as a ring; the DMA channel must be prevented
Two alternative control mechanisms are provided to detect and handle descriptor list end
(Hold) conditions:
• Hold bit control mode
• Last descriptor address control mode
The Control Mode applies to all DMA channels transmit and receive and is selected via
bit ’CMODE’ in Global Mode Register GMODE.
An HDLC frame may be contained in one buffer connected to one descriptor or it may
be contained in several buffers each associated with linked descriptors. A ’frame end’
indication (FE bit) will be set in each descriptor which points to the last buffer of one
HDLC frame.
The ’frame end’ indications are stored in the internal FIFOs influencing the FIFO control
(threshold) mechanisms. Therefore ’frame end’ indications (FE bit) are also used in non
frame oriented protocol modes such as ASYNC mode. They are referred to as ’frame
end/block end’ indication in the following chapters.
Data Sheet
allocated and the ’next descriptor address’ field of the last descriptor is invalid when
read by the DMA controller;
therefore no further receive descriptor is allocated and the ’next descriptor address’
field of the last descriptor is invalid when read by the DMA controller;
from branching a descriptor which is not yet serviced by the CPU.
(See “DMAC Operation Using Hold-Bit Control Mechanism” on page 76.)
(See “DMAC Operation Using Last Descriptor Address Control Mode” on page 78.)
65
DMA Controller and Central FIFOs
PEB 20534
PEF 20534
2000-05-30