PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 212

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Table 35
Step
No Host action has to be performed in case of a receive data overflow event. The
DSCC4 marks the receive descriptor (data section) containing incomplete data with an
’RDO’ indication in the receive status byte (RSTA). The DMA controller proceeds with
the next receive descriptor; no difference to handling of a non-exceptional frame.
Table 36
Step
1
2
3
4
5
Data Sheet
Action by Host
HOLD bit ctrld.
Action by Host
HOLD bit ctrld.
Prepare linked list for future data
transmission in shared memory.
Set HOLD=’1’ in
last element of
linked list.
Initialize CHiCFG register
- Interrupt Mask:
- DMAC Command (RDT)
Reset
CMDR.XRES.
-
Update BTDA.
Initialize CHiCFG register
- Interrupt Mask:
- DMAC Command (IDT and AR)
(RFI, TFI, RERR, TERR)
(RFI, TFI, RERR, TERR)
Exceptional handling in Case of Receive Data Overflow
Exceptional handling in Case of Transmit Data Underrun
transmitter
-
Write last transmit
descriptor
address in LTDA
register.
LTDx/FTDx ctrld.
LTDx/FTDx ctrld.
in
SCC
212
via
Action by DSCC4
Action by DSCC4
SCC starts requesting for transmit
data from central TFIFO.
SCC gets new data (if available) from
the
transmission starts.
Reset and Initialization Procedure
central
TFIFO
PEB 20534
PEF 20534
and
2000-05-30
Data