z16f2811 ZiLOG Semiconductor, z16f2811 Datasheet - Page 129

• Manufacturer Part Number: z16f2811
• Description: High Performance Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS022006-0207
PWM Reload Event
PWM Prescaler
PWM Period and Count Resolution
PWM Output Polarity and Off-State
The default off-state and polarity of the PWM outputs are controlled by the option bits
PWMHI and PWMLO. The PWMHI option controls the off-state and polarity for PWM
high-side outputs PWMH0, PWMH1, and PWMH2. The PWMLO option controls the
off-state and polarity for low-side outputs PWML0, PWML1, and PWML2.
The off-state is the value programmed in the option bit. For example, programming
to 1 makes the off-state of PWMH0, PWMH1, and PWMH2 a High logic value and the
active state a Low logic value. Conversely, programming PWMHI to 0 causes the off-state
to be a Low logic value. PWMLO is programmed in a similar manner.
PWM Enable
The MCEN option bit enables output pairs PWM0, PWM1, and PWM2. If the Motor
Control option is not enabled, the PWM outputs remain in a high-impedance state after reset
and is used as alternate functions like general purpose input. If the Motor Control option is
enabled, following a Power-On Reset (POR) the PWM pins enter a high impedance state. As
the internal reset proceeds, the PWM outputs are forced to the off-state as determined by the
PWMHI and PWMLO off-state option bits.
To prevent erroneous PWM pulse-widths and periods, registers that control the timing of
the output are buffered. Buffering causes all the PWM compare values to update. In other
words, the registers controlling the duty cycle, and clock source prescaler only take effect
on a PWM reload event. A PWM reload event is configured to occur at the end of each
PWM period or only every 2, 4, or 8 PWM periods by setting the RELFREQ bits in the
PWM Control 1 Register
by setting the READY bit in the
READY bit is set to 1, the buffered values take effect at the next reload event.
The prescaler decreases the PWM clock signal by factors of 1, 2, 4, or 8 with respect to the
system clock. The PRES[1:0] bit field in the
controls prescaler operation. This 2-bit PRES field is buffered so that the prescale value
only changes on a PWM Reload event.
The PWM counter operates in two modes to allow edge-aligned and center-aligned
outputs.
outputs. The mode in which the PWM operates determine the period of the PWM outputs
Figure 21
and
Figure 22
(PWMCTL1). Software indicates that all new values are ready
P R E L I M I N A R Y
PWM Control 0 Register (PWMCTL0)
on page 116 illustrate edge and center-aligned PWM
PWM Control 1 Register (PWMCTL1)
Multi-Channel PWM Timer
Product Specification
ZNEO
to 1. When the
™
Z16F Series
PWMHI
115