z16f2811 ZiLOG Semiconductor, z16f2811 Datasheet - Page 207

• Manufacturer Part Number: z16f2811
• Description: High Performance Microcontrollers
• Manufacturer: ZiLOG Semiconductor

™
ZNEO
Z16F Series
Product Specification
193
is detected in the Slave by SS changing state. The SS framing signal will lead the frame by
one SCK period. In this mode SCK will run continuously, starting with the initial SS
assertion. Frames will run back-to-back as long as software/DMA continue to provide
2
data. The I
S protocol (Inter IC Sound) is used to carry left and right channel audio data
with the SS signal indicating which channel is being sent. In Slave mode, the change in
state of SS (low to high or high to low) will trigger the start of a transaction on the next
SCK cycle.
NUMBITS[2:0]—Number of Data Bits Per Character to Transfer
This field contains the number of bits to shift for each character transfer. For information
on valid bit positions when the character length is less than 8-bits, see
ESPI Data Register
description on page 188.
000 = 8 bits
001 = 1 bit
010 = 2 bits
011 = 3 bits
100 = 4 bits
101 = 5 bits
110 = 6 bits
111 = 7 bits
SSIO—Slave Select I/O
This bit controls the direction of the SS pin. In single Master mode, SSIO is set to 1 unless
a separate GPIO pin is being used to provide the SS output function. In the SPI Slave or
Multi-Master configuration SSIO is set to 0.
0 = SS pin configured as an input (SPI Slave and Multi-Master modes)
1 = SS pin configured as an output (SPI single Master mode)
SSPO—Slave Select Polarity
This bit controls the polarity of the SS pin.
0 = SS is active low. (SSV = 1 corresponds to SS = 0)
1 = SS is active high. (SSV = 1 corresponds to SS = 1)
PS022006-0207
P R E L I M I N A R Y
Enhanced Serial Peripheral Interface