z16f2811 ZiLOG Semiconductor, z16f2811 Datasheet - Page 133

• Manufacturer Part Number: z16f2811
• Description: High Performance Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS022006-0207
Synchronization of PWM and ADC
Synchronized Current-Sense Sample and Hold
PWM Timer and Fault Interrupts
Fault Detection and Protection
The ADC on the ZNEO is synchronized with the PWM period. Enabling the PWM ADC
trigger causes the PWM to generate an ADC conversion signal at the end of each PWM
period. Additionally, in CENTER-ALINGED mode, the PWM generates a trigger at the
center of the period. Setting the ADCTRIG bit in the
(PWMCTL0)
The PWM controls the current-sense input sample and hold amplifier. The signal controlling
the sample/hold is configured to always sample or automatically hold when any or all the
PWM high or low outputs are in the on state. The current-sense sample and hold is controlled
by the
The PWM generates interrupts to the ZNEO CPU during any of the following events:
•
•
The ZNEO contains hardware and software fault controls, which allow rapid deassertion
of all enabled PWM output signals. A logic Low on an external fault pin (FAULT0 or
FAULT1) or the assertion of the over current comparator forces the PWM outputs to the
predefined off-state.
Similar deassertion of the PWM outputs is accomplished in software by writing to the
PWMOFF bit in the PWM control 0 register. The PWM counter continues to operate
while the outputs are deasserted (inactive) due to one of these fault conditions.
The fault inputs are individually enabled through the PWM fault control register. If a fault
condition is detected and the source is enabled, the fault interrupt is generated. The
Fault Status Register (PWMFSTAT)
interrupt.
When a fault is detected and the PWM outputs are disabled, modulator control of the PWM
outputs are reenabled either by the software or by the fault input signal deasserting.
Selection of the reenable method is made using the
(PWMFCTL). Configuration of the fault modes and reenable methods allow
pulse-by-pulse limiting and hard shutdown. When configured in AUTOMATIC RESTART
PWM Reload—The interrupt is generated at the end of a PWM period when a PWM
PWM Fault—A fault condition is indicated by asserting any FAULT pins or by the
register reload occurs.
assertion of the comparator.
Current-Sense Sample and Hold Control Register (CSSHR0 and
enables the ADC synchronization.
P R E L I M I N A R Y
is read to determine which fault source caused the
PWM Fault Control Register
PWM Control 0 Register
Multi-Channel PWM Timer
Product Specification
ZNEO
CSSHR1).
™
Z16F Series
PWM
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