z16f2811 ZiLOG Semiconductor, z16f2811 Datasheet - Page 224

• Manufacturer Part Number: z16f2811
• Description: High Performance Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS022006-0207
Note:
7. The I
8. When one bit of address is shifted out by the SDA signal, the Transmit interrupt
9. Software responds by writing the second byte of address into the contents of the I
10. The I
11. The I
12. The I
13. The I
14. Software responds by writing the data to be written out to the I
15. The I
16. The I
17. The I
18. If more bytes remain to be sent, return to step 14.
19. Software responds by asserting the STOP bit of the I
20. The I
21. The I
If the Slave responds with a Not Acknowledge during the transfer, the I
asserts the NCKI bit, sets the
halts. Software terminates the transaction by setting either the STOP bit (end transaction)
register.
asserts.
Data register.
signal.
high period of SCL. The I
If the slave does not acknowledge the first address byte, the I
NCKI bit in the I
State register. Software responds to the Not Acknowledge interrupt by setting the
STOP bit and clearing the
from the data register, sends the STOP condition on the bus and clears the
NCKI
register (2nd address byte).
bit is sent, the Transmit interrupt asserts.
data bytes if looping) by the SDA signal.
high period of SCL. The I
If the slave does not acknowledge, see the second paragraph of step 11 above.
Transmit interrupt asserts.
2
2
2
2
2
2
2
2
2
2
bits. The transaction is complete (ignore the following steps).
C Controller loads the I
C Controller shifts the rest of the first byte of address and write bit out the SDA
C Slave sends an acknowledge by pulling the SDA signal Low during the next
C Controller loads the I
C Controller shifts the second address byte out the SDA signal. When the first
C Controller shifts out the rest of the second byte of Slave address (or ensuing
C Slave sends an acknowledge by pulling the SDA signal Low during the next
C Controller shifts the data out by the SDA signal. After the first bit is sent, the
C Controller completes transmission of the data on the SDA signal.
C Controller sends the STOP condition to the I
2
C Status register, sets the
P R E L I M I N A R Y
ACKV
2
2
TXI
C Controller sets the ACK bit in the I
C Controller sets the ACK bit in the I
2
2
bit. The I
C Shift register with the contents of the I
C Shift register with the contents of the I
bit and clears the
2
C Controller flushes the second address byte
ACKV
ACK
bit and clears the
2
2
bit in the I
C bus.
C Control register.
I2C Master/Slave Controller
Product Specification
2
C Controller sets the
ZNEO
2
C Control register.
2
2
2
C Status register.
C State register and
C Status register.
ACK
2
C Controller
™
Z16F Series
2
bit in the I
2
C Data
C Data
STOP
and
2
2
C
C
210