z16f2811 ZiLOG Semiconductor, z16f2811 Datasheet - Page 228

• Manufacturer Part Number: z16f2811
• Description: High Performance Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS022006-0207
Slave Transactions
24. If there are more bytes to transfer, the I
25. The I
26. Software responds by setting the STOP bit of the I
27. A STOP condition is sent to the I
The following sections describe Read and Write transactions to the I
configured for 7-bit and 10-bit SLAVE modes.
Slave Address Recognition
The following Slave address recognition options are supported:
•
•
•
•
General Call and STARTBYTE address recognition - If
Software address recognition - To disable the hardware address recognition, the
controller is configured for Master/Slave or Slave 7-bit address mode, the hardware
detects a match to the 7-bit Slave address defined in the I2CSLVAD register and
generates the Slave Address Match interrupt (
I
the
controller is configured for Master/Slave or Slave 10-bit address mode, the hardware
detects a match to the 10-bit Slave address defined in the I2CMODE and I2CSLVAD
registers and generates the Slave Address Match interrupt (
register). The I
with the value in the
address phase and the controller is configured for Master/Slave or Slave in either 7- or
10-bit address mode, the hardware detects a match to the General Call Address or
START byte and generates the Slave Address Match interrupt. A General Call Address
is a 7-bit address of all 0’s with the R/W bit = 0. A START byte is a 7-bit address of all
0’s with the R/W bit = 1. The
RD
byte (= 0 for General Call Address). For a General Call Address, the I
automatically responds during the address acknowledge phase with the value in the
NAK
GCA
examine each received data byte before deciding to set or clear the
byte will not be acknowledged (requirement the I
must be set = 1 prior to the reception of the address byte(s). When
received byte generates a receive interrupt (
Software must examine each byte and determine whether to set or clear the
Slave 10-bit address recognition mode - If
Slave 7-bit address recognition mode - If
2
C Controller automatically responds during the acknowledge phase with the value in
bit in the I2CISTAT register distinguishes a General Call Address from a START
NAK
bit of the I2CCTL register. If software processes the data bytes associated with the
bit, the
2
C Controller generates a NAK interrupt (NCKI bit in I2CISTAT).
bit of the I2CCTL register.
IRM
2
C Controller automatically responds during the acknowledge phase
bit is optionally set following the SAM interrupt to allow software to
NAK
P R E L I M I N A R Y
bit of the I2CCTL register.
SAM
2
C Slave.
and
2
GCA
C Controller returns to step 18.
IRM
IRM
bits are set in the I2CISTAT register. The
SAM
RDRF
= 0 during the address phase and the
= 0 during the address phase and the
2
C specification).
2
bit = 1 in I2CISTAT register). The
C Control register.
= 1 in the I2CISTAT register).
GCE
I2C Master/Slave Controller
= 1 and
SAM
Product Specification
ZNEO
2
bit = 1 in I2CISTAT
C Controller
NAK
IRM
™
IRM
Z16F Series
= 0 during the
bit. A START
2
C Controller
= 1 each
NAK
IRM
bit.
bit
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