z16f2811 ZiLOG Semiconductor, z16f2811 Datasheet - Page 222

• Manufacturer Part Number: z16f2811
• Description: High Performance Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS022006-0207
S
Address
Figure 43. Data Transfer Format - Master Write Transaction with a 7-Bit Address
Slave
The procedure for a Master transmit operation to a 7-bit addressed Slave is given below:
1. Software initializes the MODE field in the I
2. Software asserts the TXI bit of the I
3. The I
4. Software responds to the TDRE bit by writing a 7-bit Slave address plus write bit (=0)
5. Software sets the
6. The I
7. The I
8. When one bit of address is shifted out by the SDA signal, the Transmit interrupt
9. Software responds by writing the transmit data into the I
10. The I
11. The I
12. The I
13. The I
14. If more bytes remain to be sent, return to step 9.
with either 7-bit or 10-bit slave address. The MODE field selects the address width for
this node when addressed as a Slave, not for the remote Slave. Software asserts the
IEN bit in the I
to the I
register.
asserts.
high period of SCL. The I
If the slave does not acknowledge the address byte, the I
bit in the I
register. Software responds to the Not Acknowledge interrupt by setting the STOP bit
and clearing the TXI bit. The I
the STOP condition on the bus and clears the STOP and NCKI bits. The transaction is
complete (ignore the following steps).
I
sent, the Transmit interrupt asserts.
2
W=0
C Data register.
2
2
2
2
2
2
2
C interrupt asserts, because the I
C Slave sends an acknowledge (by pulling the SDA signal Low) during the next
C Controller sends the Start condition to the I
C Controller loads the I
C Controller shifts the rest of the address and write bit out the SDA signal.
C Controller loads the contents of the I
C Controller shifts the data out of through the SDA signal. When the first bit is
2
C Data register.
A
2
C Status register, sets the ACKV bit and clears the ACK bit in the I
2
C Control register.
START
Data
P R E L I M I N A R Y
bit of the I
2
C Controller sets the ACK bit in the I
2
A
2
C Shift register with the contents of the I
C Controller flushes the transmit data register, sends
2
2
C Control register.
C Control register to enable Transmit interrupts.
Data
2
C Data register is empty
2
C Mode register for Master/Slave mode
2
C Shift register with the contents of the
A
2
C Slave.
2
2
C Data register.
C Controller sets the
I2C Master/Slave Controller
Data
Product Specification
ZNEO
2
C Status register.
™
A/A
Z16F Series
2
C Data
2
C State
NCKI
P/S
208