z16f2811 ZiLOG Semiconductor, z16f2811 Datasheet - Page 225

• Manufacturer Part Number: z16f2811
• Description: High Performance Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS022006-0207
S
Figure 45. Data Transfer Format - Master Read Transaction with 7-Bit Address
or the START bit (end this transaction, start a new one). The transmit data register is
flushed automatically.
Master Read Transaction with a 7-Bit Address
Figure 45
Slave.
The procedure for a Master read operation to a 7-bit addressed Slave is as follows:
1. Software initializes the MODE field in the I2C Mode register for Master/Slave mode
2. Software writes the I
3. Software asserts the START bit of the I
4. If this is a single byte transfer, software asserts the NAK bit of the I
5. The I
6. The I
7. The I
8. The I
9. The I
10. Software responds by reading the I
Address
with 7- or 10-bit addressing (I
The MODE field selects the address width for this node when addressed as a Slave,
not for the remote Slave. Software asserts the IEN bit in the I
so that after the first byte of data has been read by the I
Acknowledge instruction is sent to the I
next high period of SCL.
If the slave does not acknowledge the address byte, the I
bit in the I
register. Software responds to the Not Acknowledge interrupt by setting the STOP bit
and clearing the TXI bit. The I
the STOP condition on the bus and clears the STOP and NCKI bits. The transaction is
complete (ignore the following steps).
signal.
last, software must set the
Slave
2
2
2
2
2
illustrates the data transfer format for a read operation to a 7-bit addressed
C Controller sends the START condition.
C Controller sends the address and read bit out the SDA signal.
C Slave acknowledges the address by pulling the SDA signal Low during the
C Controller shifts in the first byte of data from the I
C Controller asserts the Receive interrupt.
2
C Status register, sets the
R=1
2
C Data register with a 7-bit Slave address plus the read bit (=1).
P R E L I M I N A R Y
NAK
A
2
2
C bus protocol allows mixing Slave address types).
bit of the I
C Controller flushes the transmit data register, sends
2
C Data register. If the next data byte is to be the
ACKV
Data
2
2
C Control register.
C Slave.
2
C Control register.
bit and clears the
A
2
C Controller, a Not
2
C Controller sets the NCKI
I2C Master/Slave Controller
2
C Slave on the SDA
Product Specification
Data
ACK
2
ZNEO
C Control register.
bit in the I
2
C Control register
™
Z16F Series
A
2
C State
P/S
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