z16f2811 ZiLOG Semiconductor, z16f2811 Datasheet - Page 68

• Manufacturer Part Number: z16f2811
• Description: High Performance Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS022006-0207
Table 17. External Interface Timing for a Read Operation - ISA Mode
Parameter
T
T
T
T
T
T
T
T
T
T
T
T
T
T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
External Interface Read Timing - ISA Mode
Figure 14
performing a Read operation in ISA mode. In
state generator has been configured to provide 2 Wait states during Read operations.
In
configured for active Low operation. The Read signal (RD) timing is shown for both
NORMAL and ISA modes.
Abbreviation
XIN Rise to Address Valid Delay
XIN Rise to Address Output Hold Time
Data Input Valid to XIN Rise Setup Time
XIN Rise to Data Input Hold Time
XIN Rise to CS Assertion Delay
XIN Rise to CS Deassertion Hold Time
XIN Fall to RD Assertion Delay
XIN Fall to RD Deassertion Hold Time
WAIT Input Pin Assertion to XIN Rise Setup Time
WAIT Input Pin Deassertion to XIN Rise Setup Time
XIN Rise to DMAACK Assertion Delay
XIN Rise to DMAACK Deassertion Hold Time
XIN Rise to BHEN or BLEN Assertion Delay
XIN Rise to BHEN or BLEN Deassertion Hold Time
Figure 14
on page 55 and
on page 55, it is also assumed that the chip select (CS) signals have been
Table 17
P R E L I M I N A R Y
provide timing information for the external interface
Figure 14
on page 55, it is assumed the Wait
Minimum
3
3
3
3
1
1
3
3
Delay (ns)
Product Specification
ZNEO
Maximum
External Interface
™
10
10
10
10
10
3
Z16F Series
54