z16f2811 ZiLOG Semiconductor, z16f2811 Datasheet - Page 167

• Manufacturer Part Number: z16f2811
• Description: High Performance Microcontrollers
• Manufacturer: ZiLOG Semiconductor

Table 83. LIN-UART Status 0 Register – LIN Mode (UxSTAT0)
PS022006-0207
RESET
FIELD
ADDR
BITS
R/W
RDA
R
7
0
0 = No break occurred.
1 = A break occurred.
TDRE—Transmitter Data Register Empty
This bit indicates that the transmit data register is empty and ready for additional data.
Writing to the transmit data register resets this bit.
0 = Do not write to the transmit data register.
1 = The transmit data register is ready to receive an additional byte to be transmitted.
TXE—Transmitter Empty
This bit indicates that the transmit shift register is empty and character transmission is
finished.
0 = Data is currently transmitting.
1 = Transmission is complete.
CTS—CTS signal
When this bit is read it returns the CTS signal level. If
replaced by the internal receive data Available signal to provide flow control in loopback
mode. CTS only affects transmission if the
RDA—Receive Data Available
This bit indicates that the receive data register has received data. Reading the receive data
register clears this bit.
0 = The receive data register is empty.
1 = There is a byte in the receive data register.
PLE—Physical Layer Error
This bit indicates that transmit and receive data do not match when a LIN slave or master is
transmitting. This is caused by a fault in the physical layer or multiple devices driving the
bus simultaneously. Reading the status 0 register or the receive data register clears this bit.
0 = Transmit and receive data match.
1 = Transmit and receive data do not match.
PLE
R
6
0
OE
R
5
0
P R E L I M I N A R Y
FF-E201H, FF-E211H
FE
R
4
0
CTSE
BRKD
R
3
0
bit = 1.
LBEN
TDRE
R
2
1
=
1
, the CTS input signal is
Product Specification
ZNEO
TXE
1
R
1
™
Z16F Series
LIN-UART
ATB
R
0
0
153