z16f2811 ZiLOG Semiconductor, z16f2811 Datasheet - Page 166

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z16f2811

Manufacturer Part Number
z16f2811
Description
High Performance Microcontrollers
Manufacturer
ZiLOG Semiconductor
Datasheet

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Table 82. LIN-UART Status 0 Register – Standard UART Mode (UxSTAT0)
PS022006-0207
RESET
FIELD
ADDR
BITS
R/W
LIN-UART Status 0 Register
RDA
R
7
0
The LIN-UART Status 0 register identifies the current LIN-UART operating configuration
and status.
Table 83
RDA—Receive Data Available
This bit indicates that the LIN-UART receive data register has received data. Reading the
LIN-UART receive data register clears this bit.
0 = The LIN-UART receive data register is empty.
1 = There is a byte in the LIN-UART receive data register.
PE—Parity Error
This bit indicates that a parity error has occurred. Reading the receive data register clears
this bit.
0 = No parity error occurred.
1 = A parity error occurred.
OE—Overrun Error
This bit indicates that an overrun error has occurred. An overrun occurs when new data is
received and the receive data register has not been read. Reading the receive data register
clears this bit.
0 = No overrun error occurred.
1 = An overrun error occurred.
FE—Framing Error
This bit indicates that a framing error (no Stop bit following data reception) is detected.
Reading the receive data register clears this bit.
0 = No framing error occurred.
1 = A framing error occurred.
BRKD—Break Detect
This bit indicates that a break has occurred. If the data bits, parity/multiprocessor bit, and
Stop bit(s) are all zeros then this bit is set to 1. Reading the receive data register clears this
bit.
on page 153 describes the Status 0 register for LIN mode.
PE
Table 82
R
6
0
below describes the Status 0 register for standard UART mode.
OE
R
5
0
P R E L I M I N A R Y
FF-E201H, FF-E211H
FE
R
4
0
BRKD
R
3
0
TDRE
R
2
1
Product Specification
ZNEO
TXE
1
R
1
Z16F Series
LIN-UART
CTS
X
R
0
152

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