z16f2811 ZiLOG Semiconductor, z16f2811 Datasheet - Page 195

• Manufacturer Part Number: z16f2811
• Description: High Performance Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS022006-0207
SCK (SSMD = 00,
Rx Data Register
Tx Data Register
Shift Register
MOSI, MISO
ESPI Interrupt
CLKPOL = 0,
PHASE = 0,
SSPO = 0)
RDRF
TDRE
I2S (Inter-IC Sound) Mode
This mode is selected by setting the SSMD field of the mode register to 010. The
and
Figure 38
of a fixed number of data bytes as defined in the DMA buffer descriptor or by software.
I
The SSV indicates whether the corresponding bytes are left or right channel data. The
SSV value must be updated when servicing the TDRE interrupt/request for the first byte in
a left or write channel frame. This is accomplished by performing a word write when
writing the first byte of the audio word, which updates both the ESPI data and transmit
data command words or by doing a byte write to update SSV followed by a byte write to
the data register. The SS signal leads the data by one SCK period.
If a DMA channel is controlling data transfer, each sequence of left (or right) channel byte
is considered a frame with a buffer descriptor. The SSV bit is defined in the buffer
descriptor command field and is automatically written to the transmit data command
2
S (Inter-IC Sound) mode is typically used to transfer left or right channel audio data.
Clkpol
Tx/Rx n-1
Tx n
Bit0
on page 182 with SS alternating between consecutive frames. A frame consists
bits of the control register must be set to 0. This mode is illustrated in
Rx n-1
Bit7
Figure 37. SPI mode (SSMD = 000)
Bit6
P R E L I M I N A R Y
Tx/Rx n
Tx n+1
Empty
Bit1
Enhanced Serial Peripheral Interface
Bit0
Product Specification
ZNEO
Bit7
Rx n
Tx/Rx n+1
™
Bit 6
empty
Z16F Series
Tx n+2
Phase
181