z16f2811 ZiLOG Semiconductor, z16f2811 Datasheet - Page 153

• Manufacturer Part Number: z16f2811
• Description: High Performance Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS022006-0207
Clear To Send Operation
External Driver Enable
8. Write to the LIN-UART control 0 register to:
9. Execute an
The LIN-UART is now configured for interrupt-driven data reception. When the LIN-
UART receiver interrupt is detected, the associated ISR performs the following:
1. Check the LIN-UART Status 0 register to determine whether the source of the
2. If the interrupt was due to data available, read the data from the LIN-UART receive
3. Execute the
The clear to send (CTS) pin, if enabled by the
register, performs flow control on the outgoing transmit data stream. The CTS input pin is
sampled one system clock before beginning any new character transmission. To delay
transmission of the next data character, an external receiver must deassert CTS at least one
system clock cycle before a new data transmission begins. For multiple character
transmissions, this operation is typically performed during the Stop bit transmission. If
CTS deasserts in the middle of a character transmission, the current character is sent
completely.
The LIN-UART provides a Driver Enable (DE) signal for off-chip bus transceivers. This
feature reduces the software overhead associated with using a GPIO pin to control the
transceiver when communicating on a multi-transceiver bus such as RS-485.
Driver Enable is a programmable polarity signal which envelopes the entire transmitted
data frame including parity and stop bits as illustrated in
signal asserts when a byte is written to the LIN-UART transmit data register. The DE signal
asserts at least one bit period and no greater than two bit periods before the Start bit is
transmitted. This allows a set-up time to enable the transceiver. The DE signal deasserts
one system clock period after the last
allows both time for data to clear the transceiver before disabling it, as well as the ability to
determine if another character follows the current character. In the event of back to back
characters (new data must be written to the transmit data register before the previous
character is completely transmitted) the DE signal is not deasserted between characters.
The DEPOL bit in the LIN-UART control register 1 sets the polarity of the DE signal.
(a) Set the receive enable bit (
(b) Enable parity, if MULTIPROCESSOR mode is not enabled, and select either
interrupt is error, break, or received data.
data register. If operating in MULTIPROCESSOR (9-bit) mode, further actions are
required depending on the MULTIPROCESSOR mode bits
even- or odd-parity.
EI
IRET
instruction to enable interrupts.
instruction to return from the ISR and await more data.
P R E L I M I N A R Y
REN
Stop
) to enable the LIN-UART for data reception
bit is transmitted. This one system clock delay
CTSE
bit of the LIN-UART control 0
Figure 26
MPMD[1:0]
Product Specification
ZNEO
on page 140. The DE
™
Z16F Series
.
LIN-UART
139