z16f2811 ZiLOG Semiconductor, z16f2811 Datasheet - Page 199

• Manufacturer Part Number: z16f2811
• Description: High Performance Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS022006-0207
Error Detection
From Master
From Master
From Master
Error events detected by the ESPI block are described in this section. Error events
generate an ESPI interrupt and set a bit in the ESPI status register. The error bits of the
ESPI Status register are read/write 1 to clear.
Transmit Underrun
A transmit underrun error occurs for a master with SSMD = 10 or 11 when a character
transfer completes and TDRE = 1. In these modes when a transmit underrun occurs the
transfer is aborted (SCK will halt and SSV will be deasserted). For a master in SPI mode
(
register to be written.
In SLAVE mode, a transmit underrun error occurs if TDRE = 1 at the start of a transfer.
When a transmit underrun occurs in SLAVE mode, ESPI transmits a character of all 1s.
A transmit underrun sets the TUND bit in the ESPI status register to 1. Writing 1 to TUND
clears this error flag.
Mode Fault (Multi-Master Collision)
A mode fault indicates when more than one master is trying to communicate at the same
time (a multi-master collision) in SPI mode. The mode fault is detected when the enabled
master’s SS input pin is asserted. For this to happen the control and mode registers must
be configured with MMEN = 1, SSIO = 0 (SS is an input) and SS input = 0. A mode fault
sets the COL bit in the ESPI status register to 1. Writing a 1 to COL clears this error flag.
SSMD = 00
To Master
) a transmit underrun is not signaled since SCK will pause and wait for the data
Figure 41. ESPI Configured as an SPI Slave
SS
MISO
MOSI
SCK
P R E L I M I N A R Y
Bit 7
8-bit Shift Register
SPI Slave
Bit 0
Enhanced Serial Peripheral Interface
Product Specification
ZNEO
™
Z16F Series
185