z16f2811 ZiLOG Semiconductor, z16f2811 Datasheet - Page 134

• Manufacturer Part Number: z16f2811
• Description: High Performance Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PWM Control Register Definitions
PS022006-0207
PWM Operation in CPU HALT Mode
PWM Operation in CPU STOP Mode
Observing the State of PWM Output Channels
PWM High and Low Byte Registers
mode, the PWM outputs are re-engaged at beginning of the next PWM cycle (master timer
value is equal to 0) if all fault signals are deasserted. In software controlled restart, all fault
inputs must be deasserted and the fault flags must be cleared.
The fault input pin is Schmitt-triggered. The input signal from the pin as well as the
comparators pass though an analog filter to reject high-frequency noise.
The logic path from the fault sources to the PWM output is asynchronous ensuring that the
fault inputs forces the PWM outputs to their off-state even if the system clock is stopped.
When the ZNEO CPU is operating in HALT mode, the PWM continues to operate if it is
enabled. To minimize current in HALT mode, the PWM must be disabled by clearing the
PWMEN bit to 0.
When the ZNEO CPU is operating in STOP mode, the PWM is disabled as the system
clock ceases to operate in STOP mode. The PWM output remains in the same state as they
were prior to entering the STOP mode. In normal operation, the PWM outputs must be
disabled by software prior to the CPU entering the STOP mode. A fault condition detected
in STOP mode forces the PWM outputs to the predefined off-state.
The logic value of the PWM outputs is sampled by reading the PWMIN register. If a
PWM channel pair is disabled (option bit is not set), the associated PWM outputs are
forced to high impedance and are used as general purpose inputs.
The following sections describe the various PWM control registers.
The PWM high and low byte (PWMH and PWML) registers (see
contain the current 12-bit PWM count value. Reads from PWMH stores the value in
PWML to a temporary holding register. A read from PWML always returns this temporary
register value. It is not recommended to write to the PWM high and low byte registers
when the PWM is enabled. There are no temporary holding registers for Write operations,
so simultaneous 12-bit writes are not possible. When either the PWM high and low byte
registers are written during counting, the 8-bit written value is placed in the counter (High
or Low Byte) at the next clock edge. The counter continues counting from the new value.
P R E L I M I N A R Y
Multi-Channel PWM Timer
Product Specification
Table 64
ZNEO
™
and
Z16F Series
Table
65)
120