z16f2811 ZiLOG Semiconductor, z16f2811 Datasheet - Page 311

no-image

z16f2811

Manufacturer Part Number
z16f2811
Description
High Performance Microcontrollers
Manufacturer
ZiLOG Semiconductor
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
z16f2811AL20AG
Manufacturer:
Zilog
Quantity:
10 000
Part Number:
z16f2811AL20EG
Manufacturer:
Zilog
Quantity:
10 000
Part Number:
z16f2811AL20SG
Manufacturer:
VISHAY
Quantity:
9 487
Part Number:
z16f2811AL20SG
Manufacturer:
Zilog
Quantity:
10 000
Part Number:
z16f2811AL20SG
Manufacturer:
ZILOG
Quantity:
20 000
Part Number:
z16f2811FI20AG
Manufacturer:
Zilog
Quantity:
10 000
Part Number:
z16f2811FI20EG
Manufacturer:
Zilog
Quantity:
10 000
Part Number:
z16f2811FI20SG
Manufacturer:
Zilog
Quantity:
155
PS022006-0207
Serial Data Format
The data format of the serial interface uses the asynchronous protocol defined in RS-232.
Each character is transmitted as 1 start bit, 8-9 data bits (least-significant bit first), and
1 stop bit
Each bit time is of same length. The bit period is set by the baud rate generator.
When the transmitter sends a character, it first sends a low start bit. The transmitter then
waits one bit time. After the start bit is sent, the transmitter sends the next data bit. The
transmitter sends each data bit in turn, waiting one full bit time before sending the next
data bit. After the last data bit is sent, the transmitter sends a high stop bit for one bit time.
The receiver looks for the falling edge of the start bit. Once the receiver sees the start bit
is low, it waits one half bit time and samples the middle of the start bit. If the middle of the
start bit is high, the receiver considers this as a false start bit. The receiver ignores a false
start bit and searches for another falling edge. If the middle of the start bit is low, the
receiver considers the start bit valid. The receiver will wait a full bit time from the middle
of the start bit to sample the next data bit. The next data bit is sampled in the middle of the
bit period. The receiver repeats this operation for each data bit, waiting one full bit time to
between sampling each data bit.
After the receiver has sampled the last data bit, it waits one full bit time and sample the
middle of the stop bit. If the stop bit is low, the receiver detects a framing error. If the stop
Figure 63. Interfacing the serial pin with an RS-232 Interface (2)
ST = Start Bit
SP = Stop Bit
D0-D7 = Data Bits
RS232 TX
RS232 RX
ST
(Figure 64
D0
Figure 64. OCD Serial Data Format
D1
on page 297).
RS-232
Tranceiver
P R E L I M I N A R Y
D2
D3
Open-Drain
Buffer
D4
D5
Vdd
10kOhm
D6
DBG pin
D7
SP
Product Specification
ZNEO
On-Chip Debugger
Z16F Series
297

Related parts for z16f2811