z16f2811 ZiLOG Semiconductor, z16f2811 Datasheet - Page 139
z16f2811
Manufacturer Part Number
z16f2811
Description
High Performance Microcontrollers
Manufacturer
ZiLOG Semiconductor
Datasheet
1.Z16F2811.pdf
(383 pages)
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Table 71. PWM Control 1 Register (PWMCTL1)
PS022006-0207
Bit Position
[7:6]
RLFREQ[1:0]
[5]
INDEN
[4]
Pol2
[3]
Pol1
[2]
Pol0
[1:0]
PRES
RESET
FIELD
ADDR
BITS
R/W
PWM Control 1 Register
RLFREQ[1:0]
7
The PWM Control 1 (PWMCTL1) register controls portions of PWM operation.
Value (H)
R/W
00
00
01
10
00
01
10
11
11
0
1
1
0
1
0
1
0
6
Description
Reload Event Frequency
This bit field is buffered. Changes to the reload event frequency takes effect
at the end of the current PWM period. Reads always return the bit values
from the temporary holding register.
PWM reload event occurs at the end of every PWM period.
PWM reload event occurs once every two PWM periods.
PWM reload event occurs once every four PWM periods.
PWM reload event occurs once every eight PWM periods.
Independent PWM Mode Enable
PWM outputs operate as three complementary pairs.
PWM outputs operate as six independent channels.
Invert output polarity for channel pair PWM2.
Non-inverted polarity for channel pair PWM2.
Invert output polarity for channel pair PWM1.
Non-inverted polarity for channel pair PWM1.
Invert output polarity for channel pair PWM0.
Non-inverted polarity for channel pair PWM0.
PWM Prescaler
The prescaler divides down the PWM input clock (either the system clock or
the PWMIN external input). This field is buffered. Changes to this field take
effect at the next PWM reload event. Reads always return the values from
the temporary holding register.
Divide by 1
Divide by 2
Divide by 4
Divide by 8
INDEN
R/W
5
0
P R E L I M I N A R Y
Pol45
R/W
4
0
FF_E381H
Pol23
R/W
3
0
Pol10
R/W
2
0
Multi-Channel PWM Timer
Product Specification
ZNEO
1
PRES[1:0]
™
Z16F Series
R/W
00
0
125
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