z16f2811 ZiLOG Semiconductor, z16f2811 Datasheet - Page 239

• Manufacturer Part Number: z16f2811
• Description: High Performance Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS022006-0207
data during the reception of a byte or when shifting an address and the RD bit is set. This
bit clears by writing to the I2CDATA register.
RDRF—Receive data register full
This bit is set = 1 when the I
byte of data. When asserted, this bit causes the I
This bit clears by reading the I2CDATA register.
SAM—Slave address match
This bit is set = 1 if the I
which matches the unique Slave address or General Call Address (if enabled by the
bit in the I
achieved on both address bytes. When this bit is set, the
This bit clears by reading the I2CISTAT register.
GCA—General call address
This bit is set in Slave mode when the General Call Address or START byte is recognized
(in either 7- or 10-bit Slave mode). The
enable recognition of the General Call Address and START byte. This bit clears when
= 0 and is updated following the first address byte of each Slave mode transaction. A
General Call Address is distinguished from a START byte by the value of the RD bit (RD
= 0 for General Call Address, 1 for START byte).
RD—Read
This bit indicates the direction of transfer of the data. It is set when the Master is reading
data from the Slave. This bit matches the least-significant bit of the address byte after the
START condition occurs (for both Master and Slave modes). This bit clears when IEN = 0
and is updated following the first address byte of each transaction.
ARBLST—Arbitration lost
This bit is set when the I
(outputs a 1 on SDA and receives a 0 on SDA). The
register is read.
SPRS—Stop/Restart condition interrupt
This bit is set when the I
RESTART condition during a transaction directed to this slave. This bit clears when the
I2CISTAT register is read. Read the
whether the interrupt was caused by a STOP or RESTART condition.
NCKI—NAK interrupt
In Master mode, this bit is set when a Not Acknowledge condition is received or sent and
neither the
setting the START or STOP bits.
In Slave mode, this bit is set when a Not Acknowledge condition is received (Master
reading data from Slave), indicating the Master is finished reading. A STOP or RESTART
condition follows. In Slave mode this bit clears when the I2CISTAT register is read.
2
START
C Mode register). In 10-bit addressing mode, this bit is not set until a match is
nor the STOP bit is active. In Master mode, this bit is cleared only by
2
2
2
C Controller is enabled in Slave mode and an address is received
C Controller is enabled in Master mode and loses arbitration
C Controller is enabled in Slave mode and detects a STOP or
P R E L I M I N A R Y
2
C Controller is enabled and the I
RSTR
GCE
bit of the I2CSTATE register to determine
bit in the I
2
C Controller to generate an interrupt.
ARBLST
2
C Mode register must be set to
RD
and
bit clears when the I2CISTAT
2
I2C Master/Slave Controller
C Controller has received a
GCA
Product Specification
ZNEO
bits are also valid.
™
Z16F Series
GCE
IEN
225