HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 172

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 3 Memory Management Unit (MMU)
Note: In single virtual memory mode, entries with the same virtual page number (VPN) but
3.4
3.4.1
The unified TLB (UTLB) is so called because of its use for the following two purposes:
1. To translate a virtual address to a physical address in a data access
2. As a table of address translation information to be recorded in the instruction TLB in the event
Information in the address translation table located in external memory is cached into the UTLB.
The address translation table contains virtual page numbers and address space identifiers, and
corresponding physical page numbers and page management information. Figure 3.7 shows the
overall configuration of the UTLB. The UTLB consists of 64 fully-associative type entries. Figure
3.8 shows the relationship between the address format and page size.
Rev.7.00 Oct. 10, 2008 Page 86 of 1074
REJ09B0366-0700
Entry 0
Entry 1
Entry 2
Entry 63
of an ITLB miss
different ASIDs cannot be set in the TLB simultaneously.
TLB Functions
Unified TLB (UTLB) Configuration
ASID [7:0]
ASID [7:0]
ASID [7:0]
ASID [7:0] VPN [31:10] V
VPN [31:10]
VPN [31:10]
VPN [31:10]
Figure 3.7 UTLB Configuration
V
V
V
PPN [28:10]
PPN [28:10]
PPN [28:10]
PPN [28:10] SZ [1:0] SH C PR [1:0]
SZ [1:0]
SZ [1:0]
SZ [1:0]
SH
SH
SH
C
C
C
PR [1:0]
PR [1:0]
PR [1:0]
D
D
D
D WT
WT
WT
WT
SA [2:0]
SA [2:0]
SA [2:0]
SA [2:0] TC
TC
TC
TC