HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 751

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive-data-full interrupt (RXI)
request and receive-error interrupt (ERI) request generation when serial receive data is transferred
from SCRSR1 to SCRDR1 and the RDRF flag in SCSSR1 is set to 1.
Bit 6: RIE
0
1
Note:
Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI.
Bit 5: TE
0
1
Notes: 1. The TDRE flag in SCSSR1 is fixed at 1.
Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCI.
Bit 4: RE
0
1
Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which
*
2. In this state, serial transmission is started when transmit data is written to SCTDR1 and
2. Serial reception is started in this state when a start bit is detected in asynchronous
SCSMR1 setting must be performed to decide the transmit format before setting the TE
RXI and ERI interrupt requests can be cleared by reading 1 from the RDRF flag, or the
FER, PER, or ORER flag, then clearing the flag to 0, or by clearing the RIE bit to 0.
the TDRE flag in SCSSR1 is cleared to 0.
bit to 1.
retain their states.
mode or serial clock input is detected in synchronous mode.
SCSMR1 setting must be performed to decide the receive format before setting the RE
bit to 1.
Description
Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI)
request disabled*
Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI)
request enabled
Description
Transmission disabled *
Transmission enabled *
Description
Reception disabled *
Reception enabled *
2
1
2
1
Section 15 Serial Communication Interface (SCI)
Rev.7.00 Oct. 10, 2008 Page 665 of 1074
REJ09B0366-0700
(Initial value)
(Initial value)
(Initial value)