HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 630

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 Bus State Controller (BSC)
Conditions Under which Problem Occurs
Example: If the refresh cycle is approximately 4,096 times/64 ms, one refresh takes place every 15
µs or so. Therefore, the master mode device’s bus performance may be decreased by 3 to 21 CKIO
cycles every 15 µs or so when the master mode device responds to a bus request.
Workarounds: Methods 1. or 2. below can be used as workarounds if degradation of the bus
performance of the master mode device due to the phenomenon described above poses a problem.
Rev.7.00 Oct. 10, 2008 Page 544 of 1074
REJ09B0366-0700
a. The partial-sharing master mode is selected (BCR1.PSHR = 1).
b. Refresh is enabled for area 3 (BCR1.DRAMTP[2:0] = 010, 011, or 101; MCR.RFSH = 1;
c. Except for refresh requests, no requests to access external memory (chip-internal requests
d. MCR.TRC is set to a value other than 0 (MCR.TRC[2:0] ≠ 000).
In addition, if the master mode device is using the bus when BSREQ is asserted, BSACK may
not be asserted immediately. In this case the above problem has little effect on the master
mode device.
1. Set MCR.TRC[2:0] to 0 0 0.
2. Store the program in an area other than area 2, and insert an instruction to perform a
MCR.RMODE = 0).
by the CPU or DMAC to access areas 0 to 6) have been issued to the bus status controller
following access to the shared area, area 2.
dummy access to external memory (area 0, 1, or 3 to 6) immediately after the instruction
accessing area 2.