HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 693

MPU 3V 16K I-TEMP,PB-FREE 208-QF

HD6417750RF240DV

Manufacturer Part Number
HD6417750RF240DV
Description
MPU 3V 16K I-TEMP,PB-FREE 208-QF
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750RF240DV

Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750RF240DV
Manufacturer:
HITACHI
Quantity:
7 287
Section 14 Direct Memory Access Controller (DMAC)
Bits 63 to 61: Transmit Size (SZ2–SZ0)
• 000: Byte size (8-bit) specification
• 001: Word size (16-bit) specification
• 010: Longword size (32-bit) specification
• 011: Quadword size (64-bit) specification
• 100: 32-byte block transfer specification
• 101: Setting prohibited
• 110: Request queue clear specification
• 111: Transfer end specification
Bit 60: Read/Write (R/W)
• 0: Memory read specification
• 1: Memory write specification
Bits 59 and 58: Channel Number (ID1, ID0)
• 00: Channel 0 (demand data transfer)
• 01: Channel 1
• 10: Channel 2
• 11: Channel 3
Bits 57 and 56: Transfer Request Mode (MD1, MD0)
• 00: Handshake protocol (data bus used)
• 01: Burst mode (edge detection) specification
• 10: Burst mode (level detection) specification
• 11: Cycle steal mode specification
Bits 55 to 48: Transfer Count (COUNT7–COUNT0)
• Transfer count: 1 to 255
• 00000000: Maximum number of transfers (16M)
Bits 47 to 32: Reserved
Bits 31 to 0: Address (ADDRESS31–ADDRESS0)
• R/W = 0: Transfer source address specification
• R/W = 1: Transfer destination address specification
Notes: 1. Only the ID field is valid for channels 1 to 3.
2. To start DMA transfer by means of demand data transfer on channel 0, the initial value
of MD in the DTR format must be 01, 10, or 11.
Rev.7.00 Oct. 10, 2008 Page 607 of 1074
REJ09B0366-0700

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