HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 807

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L:
F:
From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2).
When D = 0.5 and F = 0:
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
When Using the DMAC:
• When an external clock source is used as the serial clock, the transmit clock should not be
• When SCRDR1 is read by the DMAC, be sure to set the SCI receive-data-full interrupt (RXI)
TDRE
Note: When operating on an external clock, set t > 4.
input until at least 5 peripheral operating clock cycles after SCTDR1 is updated by the DMAC.
Incorrect operation may result if the transmit clock is input within 4 cycles after SCTDR1 is
updated. (See figure 15.25)
as the activation source with bits RS3 to RS0 in CHCR.
SCK
TxD
Frame length (L = 9 to 12)
Absolute deviation of clock frequency
M = (0.5 –
M = (0.5 – 1/(2 × 16)) × 100% = 46.875% ............................................ (2)
Figure 15.25 Example of Synchronous Transmission by DMAC
t
2N
1
D0
) – (L – 0.5) F –
D1
| D – 0.5 |
D2
N
Section 15 Serial Communication Interface (SCI)
D3
(1 + F) × 100%
Rev.7.00 Oct. 10, 2008 Page 721 of 1074
D4
................ (1)
D5
D6
REJ09B0366-0700
D7