HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 804

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 15 Serial Communication Interface (SCI)
Table 15.12 SCI Interrupt Sources
Interrupt
Source
ERI
RXI
TXI
TEI
See section 5, Exceptions, for the priority order and relation to non-SCI interrupts.
15.5
The following points should be noted when using the SCI.
SCTDR1 Writing and the TDRE Flag: The TDRE flag in SCSSR1 is a status flag that indicates
that transmit data has been transferred from SCTDR1 to SCTSR1. When the SCI transfers data
from SCTDR1 to SCTSR1, the TDRE flag is set to 1.
Data can be written to SCTDR1 regardless of the state of the TDRE flag. However, if new data is
written to SCTDR1 when the TDRE flag is cleared to 0, the data stored in SCTDR1 will be lost
since it has not yet been transferred to SCTSR1. It is therefore essential to check that the TDRE
flag is set to 1 before writing transmit data to SCTDR1.
Simultaneous Multiple Receive Errors: If a number of receive errors occur at the same time, the
state of the status flags in SCSSR1 is as shown in table 15.13. If there is an overrun error, data is
not transferred from SCRSR1 to SCRDR1, and the receive data is lost.
Rev.7.00 Oct. 10, 2008 Page 718 of 1074
REJ09B0366-0700
Usage Notes
Description
Receive error (ORER, FER, or PER)
Receive data register full (RDRF)
Transmit data register empty (TDRE)
Transmit end (TEND)
DMAC
Activation
Not possible High
Possible
Possible
Not possible Low
Priority on
Reset Release