HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 296

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 7 Instruction Set
ADD #1, R0
CMP/EQ R1, R0 ; If R0 = R1, T bit is set to 1
BT TARGET
In an RTE delay slot, status register (SR) bits are referenced as follows. In instruction access, the
MD bit is used before modification, and in data access, the MD bit is accessed after modification.
The other bits—S, T, M, Q, FD, BL, and RB—after modification are used for delay slot
instruction execution. The STC and STC.L SR instructions access all SR bits after modification.
Constant Values: An 8-bit constant value can be specified by the instruction code and an
immediate value. 16-bit and 32-bit constant values can be defined as literal constant values in
memory, and can be referenced by a PC-relative load instruction.
MOV.W @(disp, PC), Rn
MOV.L
There are no PC-relative load instructions for floating-point operations. However, it is possible to
set 0.0 or 1.0 by using the FLDI0 or FLDI1 instruction on a single-precision floating-point
register.
Rev.7.00 Oct. 10, 2008 Page 210 of 1074
REJ09B0366-0700
@(disp, PC), Rn
; T bit is not changed by ADD operation
; Branches to TARGET if T bit = 1 (R0 = R1)