HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 787

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SCSSR1. When TDRE is cleared to 0, the SCI recognizes
2. After transferring data from SCTDR1 to SCTSR1, the SCI sets the TDRE flag to 1 and starts
3. The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is set to
4. The SCI monitors the TDRE flag. When TDRE is cleared to 0, the SCI recognizes that data
5. After transferring data from SCTDR1 to SCTSR1, the SCI sets the TDRE flag to 1 and starts
Figure 15.14 shows an example of SCI operation for transmission using a multiprocessor format.
that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1.
transmission.
The serial transmit data is sent from the TxD pin in the following order.
a. Start bit: One 0-bit is output.
b. Transmit data: 8-bit or 7-bit data is output in LSB-first order.
c. Multiprocessor bit: One multiprocessor bit (MPBT value) is output.
d. Stop bit(s): One or two 1-bits (stop bits) are output.
e. Mark state: 1 is output continuously until the start bit that starts the next transmission is
1, the TEND flag in SCSSR1 is set to 1, the stop bit is sent, and then the line goes to the mark
state in which 1 is output. If the TEIE bit in SCSCR1 is set to 1 at this time, a transmit-end
interrupt (TEI) request is generated.
has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1.
transmitting. If the transmit-data-empty interrupt enable bit (TIE bit) in SCSCR1 is set to 1 at
this time, a transmit-data-empty interrupt (TXI) request is generated.
The order of transmission is the same as in step 2.
sent.
Section 15 Serial Communication Interface (SCI)
Rev.7.00 Oct. 10, 2008 Page 701 of 1074
REJ09B0366-0700