HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 287

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

This problem affects applications in science and engineering where extreme precision is required.
It is limited to cases where double-precision floating-point instructions are used to handle
denormalized numbers. The problem does not affect cases where double-precision floating-point
instructions are used but denormalized numbers are treated as zero, or cases where only single-
precision floating-point instructions are used.
Examples: The problem manifests itself in either of two ways. In one type of case a. and b. the
result is incorrect when denormalized numbers are used as input. In the other c. the result is
incorrect when a denormalized number and qNaN are used as input.
a. When the input for a double-precision FDIV instruction includes a denormalized number, an
b. When the input for a double-precision FMUL instruction includes a denormalized number, an
c. When the input for a double-precision FDIV, FADD, FSUB, or FMUL instruction consists of a
Effects: The effect of the problem is greatest in cases where denormalized numbers are used as
input with a double-precision FDIV or FMUL instruction, and an incorrect value is written to a
register as a result (a or b). In particular, mathematically inappropriate values may be generated,
such as denormalized number / denormalized number = 0 or denormalized number / 0 = 0.
Workarounds: Ordinarily, workaround 1. may be used. Workaround 2. is for calculations in
science or engineering applications where extreme precision and the use of denormalized numbers
are necessary.
1. When using double-precision floating-point instructions, set FPSCR.DN to 1 to select the
2. Avoid cases where using denormalized numbers as input produce incorrect results a. and b. by
incorrect result of zero or infinity may be generated.
incorrect result of infinity may be generated.
denormalized number and qNaN, the result may be incorrect.
mode in which denormalized numbers are treated as 0.
This workaround does not result in any decrease in performance.
means of software. Refer to “Modifying Software” below for details.
(i) Save the contents of the source and destination registers (DRn).
(ii) When a double-precision FDIV instruction generates a result of zero or infinity, call a user-
Use a TRAP routine to avoid cases where an incorrect result is generated when using a
denormalized number and qNaN as input c.. Refer to “Modifying a TRAP Routine” below for
details.
(i) When the input for a double-precision FDIV, FADD, FSUB, or FMUL instruction consists
specified function for processing denormalized numbers.
of a denormalized number and qNaN, use a TRAP routine to write the value of qNaN
(H'7FF7FFFF_FFFFFFFF) to the destination register.
Rev.7.00 Oct. 10, 2008 Page 201 of 1074
Section 6 Floating-Point Unit (FPU)
REJ09B0366-0700