HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 615

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 Bus State Controller (BSC)
13.3.9
Byte Control SRAM Interface
The byte control SRAM interface is a memory interface that outputs a byte select strobe (WEn) in
both read and write bus cycles. It has 16 bit data pins, and can be connected to SRAM which has
an upper byte select strobe and lower byte select strobe function such as UB and LB.
Areas 1 and 4 can be designated as byte control SRAM interface. However, when these areas are
set to MPX mode, MPX mode has priority.
The byte control SRAM interface write timing is the same as for the normal SRAM interface.
In read operations, the WEn pin timing is different. In a read access, only the WE signal for the
byte being read is asserted. Assertion is synchronized with the fall of the CKIO clock, as for the
WE signal, while negation is synchronized with the rise of the CKIO clock, using the same timing
as the RD signal.
In 32-byte transfer such as a cache fill or copy-back, a total of 32 bytes are transferred
consecutively according to the set bus width. The first access is performed on the data for which
there was an access request, and the remaining accesses are performed on the data at the 32-byte
boundary. The bus is not released during this period.
Figure 13.74 shows an example of byte control SRAM connection to this LSI, and figures 13.75 to
13.77 show examples of byte control SRAM read cycle.
Rev.7.00 Oct. 10, 2008 Page 529 of 1074
REJ09B0366-0700