HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 670

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 14 Direct Memory Access Controller (DMAC)
Table 14.9 External Request Transfer Sources and Destinations in DDT Mode
1
2
3
4
5
6
"SRAM-type" in the table indicates an SRAM, byte control SRAM, or burst ROM setting.
Notes: The only memory interface on which single address mode transfer is possible in DDT mode
Bus Mode and Channel Priority Order
When, for example, channel 1 is transferring data in burst mode, and a transfer request is issued to
channel 0, which has a higher priority, the channel 0 transfer is started immediately.
If fixed mode has been set for the priority levels (CH0 > CH1), transfer on channel 1 is continued
after transfer on channel 0 is completely finished, whether cycle steal mode or burst mode is set
for channel 0.
If round robin mode has been set for the priority levels, transfer on channel 1 is restarted after one
transfer unit of data is transferred on channel 0, whether cycle steal mode or burst mode is set for
channel 0. Channel execution alternates in the order: channel 1 → channel 0 → channel 1 →
channel 0.
An example of round robin mode operation is shown in figure 14.11.
Since channel 1 is in burst mode (in the case of edge sensing) regardless of whether fixed mode or
round robin mode is set for the priority order, the bus is not released to the CPU until channel 1
transfer ends.
Rev.7.00 Oct. 10, 2008 Page 584 of 1074
REJ09B0366-0700
Synchronous DRAM *
External device with DACK
Synchronous DRAM
SRAM-type, MPX, PCMCIA
SRAM-type, DRAM, PCMCIA,
MPX
SRAM-type, MPX, PCMCIA
Transfer Source
is synchronous DRAM.
When performing dual address mode transfer, make the DACK output setting for the
SRAM, byte control SRAM, burst ROM, PCMCIA, or MPX interface.
1. In SH7750, the bus width must be 64 bits
2. DACK output setting in dual address mode transfer
Transfer Direction (Settable Memory Interface)
1
*
*
2
2
External device with DACK
Synchronous DRAM
SRAM-type, MPX, PCMCIA
Synchronous DRAM
SRAM-type, MPX, PCMCIA
SRAM-type, DRAM, PCMCIA,
MPX
Transfer Destination
*
*
2
2
Single
Single
Dual
Dual
Dual
Dual
Address
Mode
0 to 3
0 to 3
0 to 3
0 to 3
0 to 3
0 to 3
Usable
DMAC
Channels