HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 786

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 15 Serial Communication Interface (SCI)
Rev.7.00 Oct. 10, 2008 Page 700 of 1074
REJ09B0366-0700
Set MPBT bit in SCSSR1 to 1 and
Clear MPBT bit in SCSSR1 to 0
Read TEND flag in SCSSR1
Read TDRE flag in SCSSR1
Read TEND flag in SCSSR1
write ID data to SCTDR1
Figure 15.13 Sample Multiprocessor Serial Transmission Flowchart
Write data to SCTDR1
Clear TDRE flag to 0
Start of transmission
Clear TDRE flag to 0
All data transmitted?
End of transmission
TEND = 1?
TEND = 1?
TDRE = 1?
Yes
Yes
Yes
Yes
No
No
No
No
1. SCI status check and ID data write:
2. Preparation for data transfer: Read
3. Serial data transmission: Write the
Read SCSSR1 and check that the
TEND flag is set to 1, then set the
MPBT bit in SCSSR1 to 1 and write
ID data to SCTDR1. Finally, clear the
TDRE flag to 0.
SCSSR1 and check that the TEND
flag is set to 1, then set the MPBT bit
in SCSSR1 to 1.
first transmit data to SCTDR1, then
clear the TDRE flag to 0.
To continue data transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to SCTDR1, and then clear
the TDRE flag to 0. (Checking and
clearing of the TDRE flag is
automatic when the direct memory
access controller (DMAC) is
activated by a transmit-data-empty
interrupt (TXI) request, and data is
written to SCTDR1.)