HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 491

MPU 3V 16K I-TEMP,PB-FREE 208-QF

HD6417750RF240DV

Manufacturer Part Number
HD6417750RF240DV
Description
MPU 3V 16K I-TEMP,PB-FREE 208-QF
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750RF240DV

Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750RF240DV
Manufacturer:
HITACHI
Quantity:
7 287
Bits 12 to 10—CAS-Before-RAS Refresh RAS Assertion Period (TRAS2–TRAS0): When the
DRAM interface is set, these bits set the RAS assertion period in CAS-before-RAS refreshing.
When the synchronous DRAM interface is set, the bank active command is not issued for the
period set by the TRC[2:0]* and TRAS[2:0] bits after an auto-refresh command is issued.
Note: For setting values and the period during which no command is issued, see 22.3.3, Bus
Bit 12: TRAS2
0
1
Note:
Bit 9—Burst Enable (BE): Specifies whether burst access is performed on DRAM interface. In
synchronous DRAM access, burst access is always performed regardless of the specification of
this bit. The DRAM transfer mode depends on EDOMODE.
BE
0
1
Note:
Timing.
TRC (Bits 29 to 27): RAS precharge interval at end of refresh.
*
In fast page mode, 32-bit or 64-bit transfer with a 16-bit bus, 64-bit transfer with a 32-bit
bus.
EDOMODE
0
1
0
1
Bit 11: TRAS1
0
1
0
1
8/16/32/64-Bit Transfer
Single
Setting prohibited
Single/fast page*
EDO
Bit 10: TRAS0
0
1
0
1
0
1
0
1
RAS/DRAM
Assertion Period
2
3
4
5
6
7
8
9
Rev.7.00 Oct. 10, 2008 Page 405 of 1074
Section 13 Bus State Controller (BSC)
32-Byte Transfer
Single
Setting prohibited
Fast page
EDO
Command
Interval after
Synchronous
DRAM Refresh
4 + TRC
5 + TRC
6 + TRC
7 + TRC
8 + TRC
9 + TRC
10 + TRC
11 + TRC
REJ09B0366-0700
(Initial value)

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