HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 858

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 16 Serial Communication Interface with FIFO (SCIF)
The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L:
F:
From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2).
When D = 0.5 and F = 0:
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Rev.7.00 Oct. 10, 2008 Page 772 of 1074
REJ09B0366-0700
Synchronization
sampling timing
Data sampling
Receive data
Frame length (L = 9 to 12)
Absolute deviation of clock frequency
Base clock
(RxD2)
M = (0.5 –
M = (0.5 – 1 / (2 × 16)) × 100% = 46.875% ................................................ (2)
timing
Figure 16.13 Receive Data Sampling Timing in Asynchronous Mode
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
2N
1
Start bit
8 clocks
) – (L – 0.5) F –
16 clocks
–7.5 clocks
| D – 0.5 |
N
(1 + F) × 100%
+7.5 clocks
D0
...................... (1)
D1